NEC System Technologies Introduces CyberWorkBench, a Series of Next
Generation System LSI Design Tools
- C language-based LSI design tools aiming to become the e industry standard - |
July 21, 2006-NEC System Technologies, Ltd. and NEC Corporation announced today  CyberWorkBench (hereinafter referred to as "CWB"), a series of design tools that significantly improve LSI design efficiency. CWB's product lineup shipping dates are as below. Trial versions of CWB will start on July 24.
Behavioral Synthesizer
generates an RTL circuit from a behavioral description ( ANSI-C,SystemC ) .
First shipment: Mid-September (ANSI-C version), end of October (System C compatible option)
Interface Generator
generates interface circuits for standard buses such as AMBA-AHB.
First shipment: Mid-September
Integrated Graphical User Interface (GUI)
shows a visual analysis of the synthesized circuit and provides a unified framework in which a designer can use all CyberWorkBench tools .
First shipment: Mid-September
Simulation Model Generator for RTL
generates a fast simulation model (C++, SystemC) from RTL (Verilog-HDL,VHDL).
First shipment: Mid-September
C-level Property Checker
assures that properties given at the behavioral level hold.
First shipment: Mid-September
Hardware/Software Co-Simulator
simulates the whole system at the cycle-accurate level, which is faster than RTL simulation by up to several hundred times.
Frist shipment: End of December
C-RTL Equivalence Prover
assures that the RTL is equivalent to the behavioral C description.
First shipment: End of March 2006
Test Bench Generator
generates an RTL test bench by utilizing information obtained from behavioral-level simulation.
First shipment: End of March 2006
RT-Floor Planner
carries out global placements of RTL by utilizing information derived from behavioral synthesis.
First shipment: First half of fiscal year 2007
CWB is a series of design tools based on the "All-in-C" (*1) concept where LSI design is done entirely in C language. The main features are as follows:
| 1. | Significant reduction of description length |
| | By adopting a C language having a higher degree of abstractness in comparison with the RTL description(*2) normally utilized in conventional logic synthesizing tools, program description length is reduced to one-seventh of the original length, thus improving system LSI design efficiency. |
| 2. | Improving verification efficiency |
| | CWB's operation level simulation speed surpasses that of RTL simulation by several hundred times. Therefore, by using C language for operation-level design, verification efficiency is improved significantly. |
| 3. | Designing an entire chip |
| | CWB can easily design control circuits for which C language has previously been considered unsuitable. Therefore, an entire chip, including both control and data processing circuits, can be designed in C language. |
Since 2001, NEC has been providing a group of C language design toolsto Panasonic Systems Solutions Company (then Matsushita Communications Industrial Co.). Panasonic Systems Solutions Company used this group of C language design tools in their development of ASIC and FPGA. The transfer from algorithm development to LSI development was made smoother due to the adoption of these tools. Panasonic (Matsushita) obtained a reduction in the development cycle by moving the core verification from RT level to C level. In addition, by constructing a library of design assets assuming high-level synthesis, these products are expected to contribute to further reduction of the development cycle.
NEC System Technologies believes that CWB, a series of next generation System LSI design tools, can become the industry standard in the System LSI design market and will continue to pursue sales of these products.
| *1 "All-in-C" Concept |
| | | There are two aspects to this concept. (1) Designing all modules that constitute hardware in C language (all modules in C). (2) Both design and verification done in C language (all processes in C) |
| *2 RTL: Register Transfer Level |
| | | A level that describes circuits, including LSI, with Flip-Flop and combinational logic circuits. Conventional LSI design has been conducted at this level. Since it requires comparatively more detailed descriptions than those found in C language, there is the problem of design efficiency tending to deteriorate as the scale of the design increases. |
| *3 FPGA: Field Programmable Gate Array |
| | | Programmable LSI. *2 (CyberWorkBench) is a registered trademark of NEC Corporation in Japan. |
| *4 For product details, please refer to the URL below. |
| | | http://www.cyberworkbench.com/english/ |
| *5 The shipment dates indicated are for the Japanese market. |
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